1. Field of the Invention
This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to NOR architecture non volatile Memory Circuit (NOR-Memory) devices and fabrication methods.
2. Discussion of Background Art
Over the past 40 years, one has seen a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling” i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology.
Memory technology has enjoyed this trend, but now the gains of scaling have slowed and almost stopped. Hence, increases in memory capacity and performance have virtually stalled. There is a need to provide continuing increases in memory capacity and performance.
One way to tackle this is to increase the number of bits per memory cell, effectively increasing the capacity without increasing production cost.
As well, integration of logic and memory needs to be improved, as current methods suffer a high energy cost and large time latency during memory fetches. Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low.
There are many techniques to construct 3D stacked integrated circuits or chips including:                Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).        Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,557,632, 8,298,875, 8,642,416, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,574,929, 8,581,349, 8,642,416, 8,687,399, 8,742,476, 8,674,470, 8,803,206, 8,902,663, 8,994,404, 9,021,414, 9,023,688, 9,030,858, 9,117,749, 9,219,005; PCT application PCT/US16/52726; U.S. patent publication 2011/0092030; and U.S. patent applications, 62/077,280, 62/042,229, Ser. Nos. 13/803,437, 61/932,617, Ser. Nos. 14/607,077, 14/642,724, 62/139,636, 62/149,651, 62/198,126, 62/239,931, 62/246,054, 62/307,568, 62/297,857, Ser. Nos. 15/095,187, 15/150,395, 15/173,686, 62/383,463, and Ser. No. 15/243,941. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.        Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. No. 8,283,215, U.S. Pat. Nos. 8,163,581, 8,753,913, 8,823,122, 9,197,804; and U.S. patent application Ser. No. 14/461,539. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.        
In a land mark papers at VLSI 2007 and IEDM 2007, Toshiba presented techniques to construct 3D memories which they called—BiCS. Many of the memory vendors followed that work by variation and alternatives mostly for non-volatile memory applications, such as now being referred to as 3D-NAND. They provide an important manufacturing advantage of being able to utilize one, usually ‘critical’, lithography step for the patterning of multiple layers. The vast majority of these 3D Memory schemes use poly-silicon for the active memory cell channel which suffers from higher cell to cell performance variations and lower drive than a cell with a monocrystalline channel. In at least our U.S. Pat. Nos. 8,026,521, 8,114,757, 8,687,399, 8,379,458, and 8,902,663, these are incorporated herein by reference, we presented multiple 3D memory structures generally constructed by successive layer transfers using ion cut techniques. In this work we are presenting multiple methods and structures to construct 3D memory with monocrystalline channels constructed by alternative methods to ion cut and successive layer transfers. This structure provides the benefit of multiple layers being processed by one lithography step with many of the benefits of a monocrystalline channel, and provides overall lower construction costs.
In addition U.S. patent applications 62/208,812, 62/215,112, 62/221,618, 62/246,054, 62/266,610, 62/271,251, 62/276,953 and 62/286,362 are incorporated herein by reference.